Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.
| EP0_IN | |
| EP0_OUT | |
| EP1_IN | |
| EP1_OUT | |
| EP2_IN | |
| EP2_OUT | |
| EP3_IN | |
| EP3_OUT | |
| EP4_IN | |
| EP4_OUT | |
| EP5_IN | |
| EP5_OUT | |
| EP6_IN | |
| EP6_OUT | |
| EP7_IN | |
| EP7_OUT | |
| EP8_IN | |
| EP8_OUT | |
| EP9_IN | |
| EP9_OUT | |
| EP10_IN | |
| EP10_OUT | |
| EP11_IN | |
| EP11_OUT | |
| EP12_IN | |
| EP12_OUT | |
| EP13_IN | |
| EP13_OUT | |
| EP14_IN | |
| EP14_OUT | |
| EP15_IN | |
| EP15_OUT |